Decoded VIC-II / SID / CIA chip register view

## Summary

Read the I/O chip registers live from VICE and display them as named, decoded fields in the trace. Without this, every `STA $D011` interaction requires manually cross-referencing a C64 reference sheet. With it, the current graphics mode, sprite state, and SID voices are immediately visible.

Source: RetroDebugger (VIC, SID, CIA panels), IceBroLite (chip state views).

---

## Memory layout

| Chip | Address range | Size | Key registers |
|------|--------------|------|---------------|
| VIC-II | $D000–$D02E | 47 bytes | Sprite X/Y, $D011 (control/raster hi), $D012 (raster lo), $D015 (sprite enable), $D016, $D018 (mem pointers), $D019 (IRQ status), $D01A (IRQ enable), $D01C (sprite multicolor), $D020 (border color), $D021 (bg color) |
| SID | $D400–$D41C | 29 bytes | Voice 1–3 freq/pw/ctrl/env, filter ($D415–$D417), vol/mode ($D418), paddle/osc readback |
| CIA 1 | $DC00–$DC0F | 16 bytes | Port A ($DC00, keyboard cols / joy2), Port B ($DC01, keyboard rows / joy1), Timer A/B, TOD, ICR ($DC0D) |
| CIA 2 | $DD00–$DD0F | 16 bytes | Port A ($DD00, VIC bank bits 0–1 + serial), ICR ($DD0D), NMI source |

---

## BMP considerations

Reading I/O registers via `memory_get()` with the default `bank_id=0` returns the **CPU-visible** value (which for write-only VIC registers returns 0xFF on read). To get the real internal register values, use a bank ID that maps to the I/O bank.

`banks_available()` (`util.py:615`) returns the bank list. The I/O bank is typically named `"io"` (bank ID varies by VICE build — usually 1 or 5). Use `memory_get(0xD000, 0xD41C, bank_id=io_bank_id, side_effects=False)` to read without triggering side effects.

---

## Implementation plan

### 1. `arch.py` — chip register definitions

Add a dict of named register fields:

```python
VIC_REGISTERS = {
0xD011: ('VIC_CR1', 'Control register 1 (RST8/ECM/BMM/DEN/RSEL/YSCROLL)'),
0xD012: ('VIC_RASTER','Raster counter'),
0xD015: ('VIC_SPENA', 'Sprite enable'),
0xD018: ('VIC_MEMPTR','Memory pointers (VM/CB)'),
0xD019: ('VIC_IRR', 'Interrupt request register'),
0xD020: ('VIC_BORDER','Border color'),
0xD021: ('VIC_BG0', 'Background color 0'),
# ... full 47-entry table
}
CIA1_REGISTERS = { 0xDC00: ('CIA1_PRA', 'Port A (keyboard cols/joy2)'), ... }
# etc.
```

### 2. `commands.py` — `put_chip_registers()`

New function called from `on_stop()` and `populate_initial_state()`:

```python
IO_CHIP_PATH = 'C64.IO[{name}]'

def put_chip_registers():
vice = STATE.require_vice()
# Discover IO bank once and cache
if not hasattr(STATE, '_io_bank_id'):
banks = vice.banks_available()
io = next((b for b in banks if b['name'] == 'io'), None)
STATE._io_bank_id = io['id'] if io else 0

data = vice.memory_get(0xD000, 0xDD0F, bank_id=STATE._io_bank_id, side_effects=False)
t = STATE.trace
for addr, (name, desc) in arch.VIC_REGISTERS.items():
val = data[addr - 0xD000]
obj = t.create_object(IO_CHIP_PATH.format(name=name))
obj.set_value('_display', f'{name} = 0x{val:02X} ({desc})')
obj.set_value('value', val)
obj.insert()
# Repeat for SID, CIA1, CIA2 ranges
```

### 3. `schema.xml` — new IO container

Add under `C64`:
```xml

```
```xml

```

### 4. `methods.py` — refresh method

```python
class IOContainer(TraceObject): pass

@REGISTRY.method(action='refresh', display='Refresh Chip Registers')
def refresh_chip_registers(node: IOContainer):
commands.STATE.require_vice()
with commands.open_tracked_tx('Refresh chip registers'):
commands.put_chip_registers()
```

---

## Files to change

- `src/main/py/src/vice/arch.py` — add `VIC_REGISTERS`, `SID_REGISTERS`, `CIA1_REGISTERS`, `CIA2_REGISTERS` dicts
- `src/main/py/src/vice/commands.py` — add `put_chip_registers()`, call from `on_stop()` and `populate_initial_state()`
- `src/main/py/src/vice/schema.xml` — add `IO`, `IOContainer`, `IORegister` schemas; update `C64` schema
- `src/main/py/src/vice/methods.py` — add `IOContainer` class, `refresh_chip_registers` method