Bank-switched memory regions (ROM/IO/cartridge)

## Description

VICE reports memory banks via `BANKS_AVAILABLE` (cpu, ram, rom, io, cart, etc.). Currently `arch.py` defines a single flat 64KB RAM region, which means Ghidra always sees the RAM-underneath view of the address space.

## Proposed implementation

- Query `banks_available()` at connect time to discover available banks
- Expose ROM/IO/cartridge banks as separate overlay memory regions in Ghidra's trace
- Use the `bank_id` parameter of `memory_get` to read from specific banks
- Show what's really mapped at key address ranges:
- `$A000-$BFFF` — BASIC ROM vs RAM
- `$D000-$DFFF` — I/O vs character ROM vs RAM
- `$E000-$FFFF` — KERNAL ROM vs RAM
- Update `put_memory_regions()` and the schema to support multiple overlapping regions

## Why this matters

Without bank awareness, users can't see ROM disassembly or I/O register contents through Ghidra — they only see whatever RAM holds underneath.