Expose VICE timing registers (raster line, cycle count) in the trace

## Summary

VICE exposes timing pseudo-registers (`LIN`, `CYC`, `STOPWATCH`) via the Binary Monitor Protocol. These are invaluable for C64 game disassembly: raster line and cycle count tell you exactly where in the frame an interrupt or routine fires.

Discovered via reference to [vscode-kickass-studio](https://github.com/sanmont/vscode-kickass-studio) which reads these alongside standard CPU registers.

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## How VICE exposes them

VICE reports **all** available registers (including timing ones) via `CMD_REGISTERS_AVAILABLE` (0x83) on connect. The current `_discover_registers()` in `util.py:340-360` already reads them all and populates `reg_name_to_id` / `reg_id_to_name`. Then `registers_get()` (`util.py:457-478`) returns them all in the `{name: value}` dict.

The timing register names as returned by VICE:
| VICE name | Meaning |
|-----------|---------|
| `LIN` | Current raster line (0–311 for PAL) |
| `CYC` | Cycle counter within the current raster line |
| `STOPWATCH` | Free-running cycle stopwatch |

These are already being received — they're just silently filtered out by `arch.VICE_TO_GHIDRA_REG` in `commands.put_registers()` (`commands.py:241-254`) because they have no Ghidra 6502 language register equivalent.

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## Implementation plan

### 1. `arch.py`
Add a set of timing register names that should be displayed but NOT passed to `t.put_registers()`:
```python
VICE_TIMING_REGS = {'LIN', 'CYC', 'STOPWATCH'}
```

### 2. `commands.py` — `put_registers()` (line 230)
Currently the loop skips any register not in `VICE_TO_GHIDRA_REG`. Change the loop to:
- If `vice_name` in `VICE_TO_GHIDRA_REG`: build a `RegVal` and add to `reg_vals` (existing path)
- Elif `vice_name` in `arch.VICE_TIMING_REGS`: create the trace object and set `_display`/`value`, but **do not** add to `reg_vals` (can't be written to Ghidra language registers)

The trace object path can reuse the existing pattern:
```
C64.Threads[0].Stack[0].Registers[LIN]
C64.Threads[0].Stack[0].Registers[CYC]
C64.Threads[0].Stack[0].Registers[STOPWATCH]
```

### 3. `schema.xml`
No changes needed — the `Register` schema (`schema.xml:79-83`) is generic enough. The `RegisterContainer` element schema accepts any `Register` object.

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## Display format suggestion
```
LIN = 251 (raster line)
CYC = 42 (cycle)
STOPWATCH = 1234567
```

---

## Files to change
- `src/main/py/src/vice/arch.py` — add `VICE_TIMING_REGS`
- `src/main/py/src/vice/commands.py` — update `put_registers()` loop (~line 241)