RISC-V port implementation

I want to announce that we are currently working on RISC-V implementation using vector extension.
As we I mean: Samsung R&D Poland + partially RISE Project engineers

Code is being developed on feature branch at: https://github.com/k-kisielak/opus/tree/rvv_impl
Implementation is in early stage and is not deemed for merging in current form.

Current state:
We started with implementing parts of silk module:

• basing on existing SSE implementation we prepared one using RISC-V vector intrinsics

Items under development:

• tests are to be performed, both functional and performance ones - to test those changes we have access to RISC-V devices like BananaPI F3, we have experience with testing RVV under qemu
• we are looking into expanding github action configs to allow testing RISC-V version (as of now only on linux)
• we are integrating more RVV implementations, namely for burg modified algorithm

We would gladly accept any feedback, thank you!

Start with the rvv_impl feature branch and its RISC-V vector-intrinsic implementation of the silk module, comparing it with the existing SSE implementation. Review the planned functional and performance tests on RISC-V devices or QEMU, GitHub Actions Linux testing, and the burg modified algorithm work; completion is not defined because the issue says the implementation is still early and not ready to merge.