Track SHAKTI, XiangShan, and T-Head RISC-V target profiles

## Goal

Track explicit Linux RISC-V implementation profiles for SHAKTI, XiangShan, and T-Head/XuanTie, whose roadmap suites were added by #457.

## Scope

- Record the exact base ISA, standard extensions, vendor extensions, ABI, and privilege/runtime requirements for each profile.
- Keep SHAKTI core-class differences explicit instead of assuming every core is RV64 Linux-capable.
- Model XiangShan vector/cache tuning separately from the portable RISC-V ISA contract.
- Model T-Head `XThead*` vendor extensions with clear feature names and assembler diagnostics.
- Produce backend-neutral fixtures and split implementation into focused child issues when the profile schema is ready.

## Completion criteria

- Each project maps to a documented RISC-V base/profile combination.
- No vendor instruction is silently enabled for generic `riscv64`.
- Feature detection and invalid-combination tests exist.
- Manifest cells are activated independently as their contracts become executable.

Related: #93, #368, #457

Start by reading the related issues #93, #368, and #457, including the roadmap suites added by #457, then define the profile schema before splitting implementation into focused child issues. Add backend-neutral fixtures, feature-detection and invalid-combination tests, and activate manifest cells independently as each SHAKTI, XiangShan, and T-Head contract becomes executable.

Written by the indexing model from the issue text.