Investigate RCsc/RCpc for weak on strong memory emulation
Open
enhancement
qemu
- Dominant language
- Swift
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Description
Latest A-series chips and M1 support ARM “Release Consistency sequentially consistent“ and “Release Consistent processor consistent” instructions. By emitting them in JIT in place of standard STR instructions, we can enable error-free multicore emulation of x86_64 on ARM64. RCpc seems to be the better of the two.
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