ucb-bar / ucb-bar/berkeley-hardfloat
How to compile it to verilog!
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- Dominant language
- Scala
- Stars
- 393
- Forks
- 111
- PR merge metrics
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Description
Hi,
I have installed sbt on my windows machine, and when I run make it would generate these errors,
git submodule update --init berkeley-testfloat-3
fatal: not a git repository (or any of the parent directories): .git
make: *** [Makefile:9: berkeley-testfloat-3/.git] Error 128
So How should I Generate Verilog for implementation of FPGA?
Contributor guide
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with Makefile:9 and the reported sbt and Windows build steps to determine how the repository expects its submodule to be initialized. Document the supported commands and prerequisites for generating Verilog for FPGA implementation, including how to avoid the reported non-repository error.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- build-system
- Issue type
- Documentation
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100