ucb-bar / ucb-bar/berkeley-hardfloat
verilog simulator
Open
Nobody has claimed this yet.
- Dominant language
- Scala
- Stars
- 393
- Forks
- 111
- PR merge metrics
- No merged PRs in 30d
Description
It would be good to make Verilog testing independent from commercial tools - Synopsys VCS. A potential solution would be to use verilator instead.
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the repository's Verilog testing setup and the commands that invoke Synopsys VCS. Investigate whether Verilator can replace that invocation and identify any compatibility gaps. Done means the existing Verilog tests run successfully without commercial tools; no specific files or tests are named in the issue.
Written by the indexing model from the issue text.
Assessment
- Domain
- build-system, testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 25/100