TODO: document user-facing core and props features merged August 20-29, 2026

Audit scope

This tracks user-facing documentation gaps found by reviewing:

• the latest 80 merged PRs in tscircuit/core (August 22-29, 2026),
• merged PRs in tscircuit/props from August 20-29, 2026, and
• current tscircuit/docs pages, open issues, and open PRs at 6dfe16c.

The checklist is grouped into focused, independently reviewable docs PRs. Each PR should use Part of #<this issue> so this issue stays open until every track is merged.

Prefer concise additions to existing property tables or nearby prose. Add a dedicated section only for a new element or a workflow whose contract cannot be explained safely in a table row.

TODO

1. Schematic sheet sizing and graphics

Sources: tscircuit/core#3458, tscircuit/core#3460, tscircuit/props#818, tscircuit/props#819, tscircuit/props#820

PR: #855

• Add an element reference for <schematicgraphic /> covering imageUrl, svgContent, fallback behavior, SVG-only input, and optional dimensions.
• Document <schematicsheet sheetSize="A4" | "ANSI_B"> and explicit sheetWidth / sheetHeight overrides.
• Correct the current sheet props table: name is optional and unnamed sheets receive generated names.
• Include a runnable diagram-only sheet example and cross-link the two element pages.

2. Board stackup, routing, pours, and castellated edges

Sources: tscircuit/core#3362, tscircuit/core#3439, tscircuit/props#808, tscircuit/props#816, tscircuit/props#817, tscircuit/core#3104

PR: #850

• Document automaticPoursEnabled, its default, eligible power nets, and its routing prerequisites.
• Document allowBlindAndBuriedVias, its default, and how it changes autorouter via spans.
• Document castellated outline vertices: isCastellatedHole, required diameters, optional connectivity, and board-pinout behavior.
• Correct supported board layers to include layers={10} and close the docs gap reported by tscircuit/core#3104.

3. Schematic labels and compact passive symbols

Sources: tscircuit/core#3416, tscircuit/core#3430, tscircuit/core#3438, tscircuit/props#810, tscircuit/props#814

PR: #856

• Document <netlabel inline />, automatic placement, ignored anchor props, and anchored fallback behavior.
• Document <port schPinLabelFontSize="sm" | "default" | Distance>.
• Update resistor and capacitor schSize docs for the new "sm" and "xs" compact premade symbols and their current limitations.

4. Schematic-box pin-style inheritance

Sources: tscircuit/core#3412, tscircuit/core#3413, tscircuit/props#813

PR: #851

• Add schPinStyle to the <schematicbox /> props reference.
• Explain inheritance from the chipRef component, local pin-number/label keys, field-by-field overrides, and using 0 to clear inherited margins.

5. Fanout controls and singleton buses

Sources: tscircuit/props#811, tscircuit/props#812, tscircuit/props#824

PR: #857

• Document fanoutMargin on <breakout />.
• Document canonical edge-first fanout directions and their PCB-world coordinate semantics while noting legacy names remain accepted.
• Correct <bus /> to allow one or more connections and add a singleton control-net example.

6. Custom implicit breakout-point solvers

Sources: tscircuit/core#3370, tscircuit/props#807, tscircuit/props#809

PR: #852

• Extend the custom-autorouter guide with implicitBreakoutPointSolverFn.
• Document the synchronous-only callback, input regions/connections/buses/boundary spacing, the current externalDestination limitation, exact output cardinality, and breakout-point shape.
• Include a small typed implementation example.

7. Disable analog simulation at the platform/project level

Sources: tscircuit/core#3493, tscircuit/props#823

PR: #853

• Add analogSimulationDisabled to the platform configuration reference.
• Explain that it is available at the project/platform level and skips SPICE-model processing, validation, and simulator execution.

8. Pin-header installation direction

Source: tscircuit/props#805

PR: #854

• Document connectsFromAbove and connectsFromBelow as mating-side aliases for top/bottom layer.
• Explain explicit-layer precedence and the mutually exclusive aliases.

Already covered (do not duplicate)

• Antenna element and WiFi guide: tscircuit/docs#848
• Preferred bus routing layers: tscircuit/docs#845
• JST connector standards: tscircuit/docs#843
• Copper-pour thermal reliefs: tscircuit/docs#842
• Via-in-pad: tscircuit/docs#841
• Earlier platform configuration options: tscircuit/docs#836
• Earlier BGA fanout and breakout behavior: tscircuit/docs#831, tscircuit/docs#833, tscircuit/docs#834

Dependency bumps, solver fixes without a new public API, test fixtures, and debug-only Circuit JSON are intentionally outside this documentation pass.

Validation for every PR

• bun run format:check
• bun run typecheck
• bun run build
• git diff --check
• New TSX examples checked against a tscircuit release containing the documented API (Docusaurus does not compile preview strings).

Choose one of the eight independently reviewable tracks, then read its cited tscircuit/core and tscircuit/props changes alongside the current tscircuit/docs pages. Use the track checklist as the completion criteria and validate each focused PR with bun run format:check, bun run typecheck, bun run build, git diff --check, and a release-compatible check of any new TSX examples.