schPinArrangement with leftPinCount/rightPinCount creates zero schematic ports

Start in NormalComponent._addChildrenFromStringOrProps around line 335 and inspect getSizeOfSidesFromPortArrangement, then trace how getAllDimensionsForSchematicBox uses the result. Compare the deprecated Size and current PinCount arrangements, including top and bottom sides; done means both produce matching schematic ports and box placement, while underscorifyPortArrangement remains consistent.

Summary

schPinArrangement written with the current ...PinCount field names produces a chip with zero schematic ports. The deprecated ...Size names work.

<chip name="U1" footprint="soic8" schPinArrangement={{ leftPinCount: 4, rightPinCount: 4 }} />

No error is raised. The chip renders with a schematic body and no pins, which looks like a symbol problem rather than a prop that was silently dropped. It's also worse than passing nothing — omitting schPinArrangement entirely gives you 8 ports.

...PinCount is not an invented spelling. @tscircuit/props declares both, and marks the Size fields as deprecated in favour of PinCount:

// schematicPortArrangement in @tscircuit/props
leftSize: z.number().optional().describe("@deprecated, use leftPinCount"),
...
leftPinCount: z.number().optional(),

So the documented, non-deprecated spelling is the one that doesn't work.

Cause

Two places read ${side}Size without a ${side}PinCount fallback.

1. Port creation — NormalComponent._addChildrenFromStringOrProps (~line 335):

for (const side of sides) {
  const size = (schPortArrangement as any)[`${side}Size`]
  for (let i = 0; i < size; i++) { ... }
}

With leftPinCount, size is undefined, the loop body never runs, and no ports are queued.

2. Schematic box sizing — getSizeOfSidesFromPortArrangement:

const { leftSize = 0, rightSize = 0, topSize = 0, bottomSize = 0 } = pa as any
return { leftSize, rightSize, topSize, bottomSize }

Every side comes back 0, so getAllDimensionsForSchematicBox lays out a box with no pins.

Both have to be fixed — patching only the first still yields source_port 8 / schematic_port 0, because the box has nowhere to put them. I confirmed that intermediate state while tracing this.

Notably, the same file already knows about the PinCount names elsewhere:

["leftSize","rightSize","topSize","bottomSize",
 "leftPinCount","rightPinCount","topPinCount","bottomPinCount"]
  .some((key) => key in schPortArrangement)

and underscorifyPortArrangement maps leftPinCount → left_size correctly. So the support is partial: the circuit-JSON serialisation handles it, port creation and box layout don't.

Expected

{ leftPinCount: 4, rightPinCount: 4 } should behave identically to { leftSize: 4, rightSize: 4 }, including for topPinCount / bottomPinCount.

PR follows.