KiCad project export drops explicit board design-rule limits

Versions: @tscircuit/cli 0.1.2057; tscircuit 0.0.2516; KiCad 10.0.2; Bun on Linux/WSL2.

tsci build lib/index.tsx --svgs --glbs --kicad-project produces an index.kicad_pro with no board.design_settings.rules, even though the emitted pcb_board records explicitly configured fabrication limits:

{"num_layers":1,"min_trace_width":0.25,"min_board_edge_clearance":0.3}

The source board explicitly supplies minTraceWidth={0.25} and minBoardEdgeClearance={0.3}. The exported project contains no corresponding minimums. Opening the exported project and running native kicad-cli pcb drc index.kicad_pcb --format json therefore uses unrelated KiCad defaults. Our measured 0.4-mm board-edge clearance is flagged against KiCad's fallback 0.5-mm limit, rather than the declared provisional 0.3-mm project limit:

Board edge clearance violation (board setup constraints edge clearance 0.5000 mm; actual 0.4000 mm)

Expected: export explicit, representable circuit design constraints into the KiCad project (at least min_track_width and min_copper_edge_clearance), and document any unsupported mappings. Do not silently drop the source contract at interchange. A small integration fixture should set nondefault limits, export the project and verify those limits through native KiCad DRC/readback.

Local workaround: patch the generated project's rules to min_track_width=0.25, min_clearance=0.15 and min_copper_edge_clearance=0.3, then run KiCad on the complete project. No rules are suppressed and unrelated warnings remain. No upstream implementation or PR is in progress from this thread.

Start with the tsci build lib/index.tsx --svgs --glbs --kicad-project entry point and inspect the generated index.kicad_pro alongside the emitted PCB records. Add an integration fixture with nondefault limits, then run kicad-cli pcb drc index.kicad_pcb --format json and verify the exported project readback contains the supported minimums and documents unsupported mappings.