VHDL: <= is assignment (not less-than)
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Description
The <= operator is essential in VHDL, but it is an assignment operator and should be the mirror image of =>.
Is there any way to replace the ligature for VHDL specifically (by IDE or otherwise) or do I need a separate font altogether?
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue concerns the <= ligature and VHDL-specific behavior, but names no file, test, or entry point. First check the repository’s documented ligature customization options and determine whether language-specific replacement is supported; done means identifying a confirmed implementation path or documenting that a separate font is required.
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Assessment
- Domain
- design
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100