scroll-tech / scroll-tech/ceno
rv32im chip optimisation plan
Open
Nobody has claimed this yet.
- Dominant language
- Rust
- Stars
- 153
- Forks
- 43
- Avg merge
- 3d 13h
- Merged PRs (30d)
- 4
Description
Merge rv32im opcode with similar functionality into single chip, which benefits
- less kernel invoked
- less smaller layer sumcheck
which in particular aim for improve gpu utilization
opcode group
- all load/store opcodes
- branching
- logical
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
No files or tests are named; start by locating the rv32im opcode implementation and the chip, kernel, and layer-sumcheck handling. Review the load/store, branching, and logical opcode groups, then measure whether merging similar functionality reduces kernel invocations and layer sumchecks while improving GPU utilization.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- compilers, performance
- Issue type
- Refactor
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100