[PIR][WP14] Real-CSI validation + pose-semantic embedding pipeline (pick up ADR-178 gaps C & D)

Epic: #1658 · Cross-repo companion: ruvnet/RuVector#852 · Program epic: ruvnet/RuVector#837 · Plan: 03-program-plan.md in ruvnet/ruvector

Goal

Close ADR-178's two still-open gaps and validate the perception stack against real, not synthetic, CSI data:

• Gap C — CSI bridge I/Q → pose-semantics conversion.
• Gap D — mcp-brain-server-side cluster consumer.

If time and budget allow, extend into the universal / heterogeneous-chipset CSI vocabulary research bet.

Current state

The ruview-csi-bridge inside ruvnet/ruvector (crates/ruvector-hailo-cluster/src/bin/ruview-csi-bridge.rs) is explicitly transport-only — it parses RuView's ADR-018 UDP CSI frames and posts a header-summary string into the Hailo embed RPC. Its own source comment disclaims doing pose embedding.

True CSI-tensor → HEF → pose-tensor embedding needs a pose-specific HEF (the Hailo Model Zoo currently lacks one for the target chips), a generalized HailoPipeline<I,O>, and host-side I/Q preprocessing. ruvector's ADR-178 §3.2C tracks this as unbuilt, separate-ADR scope. The brain-side cluster consumer (gap D) is likewise unbuilt.

On the ruvector side, ruvector-perception is 3.8K LOC but synthetic-data-only — never validated against real captures. That validation is the companion issue, ruvnet/RuVector#852.

Existing RuView capability for context: real-time spatial intelligence, vital-sign monitoring, presence detection, Home Assistant / HomeKit / Google Home / Alexa integration, 21 entities per node (11 raw + 10 inferred semantic states such as "possible-distress" and "fall-risk-elevated"). ruvector's crates/ruvector-mmwave (Seeed MR60BHA2/LD2410 radar, ADR-063) is a useful ground-truth comparison channel.

⚠️ The universal CSI vocabulary has no prior art anywhere

The program's evidence review searched specifically and repeatedly — direct phrase search, "chipset-agnostic," "shared vocabulary," "common backbone," "tokenize" + CSI, explicit vendor-name combinations. No paper frames CSI from Realtek / Qualcomm / Nexmon / MediaTek chipsets as a shared "RF latent vocabulary" feeding one common backbone.

Good for novelty, bad for evidence backing. Do not present this as reproducing published work. Adjacent work to build on and differentiate from — motivation, never validation: arXiv:2608.14694 (wireless foundation models survey), arXiv:2604.18255 (WiFo-MiSAC), arXiv:2512.22143 (UniFi), arXiv:2605.14171 (CSI-JEPA).

Acceptance criteria

• ruvector-perception achieves a documented accuracy baseline on real CSI captures, not just synthetic.
• ADR-178 gaps C and D are closed per that ADR's own definition of done — pose-specific HEF sourced or trained, generalized HailoPipeline<I,O>, host-side I/Q preprocessing, and the mcp-brain-server-side cluster consumer built.
• Sensing accuracy is measured against mmWave/radar ground truth where available, feeding WP12's daily metric log if this lands within the acceptance window.
• If the vocabulary bet is funded: CSI from at least two distinct chipset families encodes into a shared latent space, and a downstream task trained on one chipset's data performs above a stated floor on the other's without retraining. This is the falsifiable core.
• If the vocabulary bet is funded: a negative-result criterion decided in advance — what measurement would establish the hypothesis does not hold. A research bet with no failure condition is not a research bet.
• No document produced here claims external validation for the universal-vocabulary hypothesis.

Dependencies

None — independent of the WP0–WP12 critical path. Recommend funding separately.

Start with ADR-178 and crates/ruvector-hailo-cluster/src/bin/ruview-csi-bridge.rs, then review the companion validation work in ruvnet/RuVector#852. Trace the existing transport-only CSI path and the stated gap-C and gap-D requirements. Done means documented real-CSI accuracy results plus the ADR-defined pose pipeline and brain-side consumer, with any funded vocabulary experiment reporting its cross-chipset and negative-result criteria.