Please support non-2^N SIMD lane counts

The silicon that supports these more or less directly:
GPUs handle Vec3s (f32x3 typically) all the time already.
Arm SVE supports 384-bit width vector registers and is available Soon™.
RISCVV will eventually exist and support arbitrary-width vectors, somewhere, over the rainbow🌈 someday🎵...

LLVM's approach for handling these when only fixed width vector registers are available to compile to was, as far as I could tell, and as described by the author of the vek crate, an approach similar to the one GPUs use: use 128-bit registers just fine but politely ignore the unspecified lanes when the "Vec3" types are loaded and stored.

Also the https://github.com/WebAssembly/flexible-vectors/ proposal exists, though is currently in a fairly nascent state. Still, another point to this being a long-term desirable even if it's not immediately needed.

The issue does not name a source file, test, or entry point. Start by reviewing the referenced LLVM approach and the linked vek discussion, then trace how rustc_codegen_cranelift represents and lowers SIMD types. Done would require an agreed design, implementation, and coverage for non-power-of-two lane counts.