RISC-V RVV not enabled despite `-Ctarget-cpu=native`

I tried this code

#![feature(stdarch_riscv_feature_detection)]
fn main() {
    println!("Enabled: {}", cfg!(target_feature="v"));
    println!("Detected: {}", std::arch::is_riscv_feature_detected!("v"));
}

I expected to see this happen

When building with -Ctarget-cpu=native I expect both of these to be true.

Instead, this happened

Both are false. I'm surprised that the first is false because native should mean v is enabled. I'm also surprised that the second is false, because even if not built in, it should be detected at least?

$ RUSTFLAGS="-Ctarget-cpu=native" cargo  +nightly -vvvv run
       Fresh hasvec v0.1.0 (/home/orangepi/scm/hasvec)
    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.07s
     Running `CARGO=/home/orangepi/.rustup/toolchains/nightly-riscv64gc-unknown-linux-gnu/bin/cargo CARGO_MANIFEST_DIR=/home/orangepi/scm/hasvec CARGO_MANIFEST_PATH=/home/orangepi/scm/hasvec/Cargo.toml CARGO_PKG_AUTHORS='' CARGO_PKG_DESCRIPTION='' CARGO_PKG_HOMEPAGE='' CARGO_PKG_LICENSE='' CARGO_PKG_LICENSE_FILE='' CARGO_PKG_NAME=hasvec CARGO_PKG_README='' CARGO_PKG_REPOSITORY='' CARGO_PKG_RUST_VERSION='' CARGO_PKG_VERSION=0.1.0 CARGO_PKG_VERSION_MAJOR=0 CARGO_PKG_VERSION_MINOR=1 CARGO_PKG_VERSION_PATCH=0 CARGO_PKG_VERSION_PRE='' LD_LIBRARY_PATH='/home/orangepi/scm/hasvec/target/debug/deps:/home/orangepi/scm/hasvec/target/debug:/home/orangepi/.rustup/toolchains/nightly-riscv64gc-unknown-linux-gnu/lib/rustlib/riscv64gc-unknown-linux-gnu/lib:/home/orangepi/.rustup/toolchains/nightly-riscv64gc-unknown-linux-gnu/lib:/usr/local/lib:/usr/local/lib:/usr/local/lib:/usr/local/lib' target/debug/hasvec`
Enabled: false
Detected: false

If forcing v feature on, it works as expected:

$ RUSTFLAGS="-Ctarget-cpu=native -Ctarget-feature=+v" cargo +nightly run
warning: unstable feature specified for `-Ctarget-feature`: `v`
  |
  = note: this feature is not stably supported; its behavior can change in the future

warning: `hasvec` (bin "hasvec") generated 1 warning
    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.07s
     Running `target/debug/hasvec`
Enabled: true
Detected: true

Meta

$ rustc +nightly --version --verbose
rustc 1.87.0-nightly (1aeb99d24 2025-03-19)
binary: rustc
commit-hash: 1aeb99d248e1b0069110cb03c6f1dcc7b36fd7f3
commit-date: 2025-03-19
host: riscv64gc-unknown-linux-gnu
release: 1.87.0-nightly
LLVM version: 20.1.0

Surely this CPU supports v as a whole? The instructions definitely work. Well, the ones I've tried work. It's an Orange Pi RV2.

$ cat /proc/cpuinfo 
processor       : 0
hart            : 0
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 1
hart            : 1
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 2
hart            : 2
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 3
hart            : 3
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 4
hart            : 4
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 5
hart            : 5
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 6
hart            : 6
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 7
hart            : 7
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

Start by reproducing the reported snippet with RUSTFLAGS="-Ctarget-cpu=native" on the riscv64gc target, then compare cfg!(target_feature="v") with std::arch::is_riscv_feature_detected!("v"). Use the forced -Ctarget-feature=+v result as a control; done means native handling reports the supported vector feature consistently.