How should we handle matrix ABIs?
Nobody has claimed this yet.
- Dominant language
- Rust
- Stars
- 119k
- Forks
- 16.1k
- PR merge metrics
- PR metrics pending
Description
Some CPU architectures have developed "matrix extensions". These are sometimes equivalent to "vectors, but bigger" in terms of how the ABI should be handled (reusing the same architectural state, thus having similar concerns). But not always! They may use entirely different architectural state, usually entirely "caller-save" (i.e. always "volatile" or "call-clobbered").
AArch64
Scalable Matrix Extensions
- https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-scalable-matrix-extension-introduction
- https://github.com/rust-lang/rust/issues/133146
PowerPC
MMA
x86
AMX
- https://github.com/rust-lang/rust/issues/126622
- introduces the
amx_tiletype, AKAx86_amxor__tile1024i
References
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reading the linked Rust issues 133146, 131800, and 126622, along with the ARM SME, PowerPC MMA, and x86 AMX references. Compare how each matrix extension uses architectural state and whether it introduces types such as x86's amx_tile. Done requires an agreed ABI-handling policy covering the listed architectures.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100