rust-embedded / rust-embedded/riscv
Immediate operand support for CSR instructions？
Nobody has claimed this yet.
- Dominant language
- Rust
- Stars
- 1.1k
- Forks
- 200
- Avg merge
- 11d 2h
- Merged PRs (30d)
- 2
Description
When I use riscv::register::mstatus::set_mie(); to enable global interrupts, the resulting assembly code is quite puzzling.
It does not use the csrsi instruction, but instead uses the csrs instruction.
The csrs instruction uses an additional register.
This causes two problems:
- Code bloat
- Toggling global interrupts becomes a non-atomic operation (which contradicts the RISC-V Privileges document)
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by tracing the implementation of riscv::register::mstatus::set_mie() and inspect the assembly it generates. Determine how CSR writes select between register and immediate operands, then verify that enabling interrupts uses the atomic csrsi form without the extra register or code bloat.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100