rust-embedded / rust-embedded/riscv
`riscv`: H-Mode and VS-Modes?
Open
Nobody has claimed this yet.
- Dominant language
- Rust
- Stars
- 1.1k
- Forks
- 200
- Avg merge
- 11d 2h
- Merged PRs (30d)
- 2
Description
Is it in scope to include the hypervisor extension register read/writes to this crate?
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reviewing the crate's existing register-access API and how processor modes are represented. Determine whether H-Mode and VS-Mode hypervisor register reads and writes are in scope, then define the affected register set and the tests needed to verify the agreed behavior.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 30/100