rust-embedded / rust-embedded/riscv
`riscv-rt`: example multicore.rs could cause HART to loop forever because of race condition
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Description
In the multicore.rs example, the other HARTs wait for an interrupt before entering main. However it seems as though there could be a race condition if HART 0 sets the interrupt flag to 1 in https://github.com/rust-embedded/riscv/blob/95cfb90c66fbfc0d66975a4235e1aeab96df9c39/riscv-rt/examples/multi_core.rs#L47 , and then HART 1 sets it to 0 in https://github.com/rust-embedded/riscv/blob/95cfb90c66fbfc0d66975a4235e1aeab96df9c39/riscv-rt/examples/multi_core.rs#L19.
This would make the interrupt flag be 0, when HART 1 is entering the loop in https://github.com/rust-embedded/riscv/blob/95cfb90c66fbfc0d66975a4235e1aeab96df9c39/riscv-rt/examples/multi_core.rs#L24-L29, and remain 0, because HART 0 has already set the flag, but it was overwritten by HART 1.
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
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Research direction
Start with riscv-rt/examples/multi_core.rs, especially the interrupt-flag writes around lines 19 and 47 and the wait loop at lines 24-29. Trace the ordering between HART 0 and HART 1, then verify the example cannot leave a HART looping forever and that all HARTs can enter main.
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Assessment
- Tech stack
- rust
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100