rust-embedded / rust-embedded/riscv
`riscv`: Advanced Interrupt Architecture support
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help wanted
- Dominant language
- Rust
- Stars
- 1.1k
- Forks
- 200
- Avg merge
- 11d 2h
- Merged PRs (30d)
- 2
Description
Among other things this defines a couple of CSR's for the IMSIC:
-
miselect -
mireg -
mtopei -
mtopi -
mvien -
mvip -
siselect -
sireg -
stopei -
stopi -
hvien -
hvictl -
hviprio1 -
hviprio2 -
vsiselect -
vsireg -
vstopei -
vstopi
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the existing RISC-V CSR definitions and reading how processor extensions are represented. Use the IMSIC and Advanced Interrupt Architecture specification to determine the required behavior for the listed machine, supervisor, hypervisor, and virtual-supervisor CSRs; done means all listed CSRs are supported consistently.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100