rust-embedded / rust-embedded/riscv
`riscv`: Add missing CSR's
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Nobody has claimed this yet.
help wanted
- Dominant language
- Rust
- Stars
- 1.1k
- Forks
- 200
- Avg merge
- 11d 2h
- Merged PRs (30d)
- 2
Description
- mpu
- mdelet /mideleg
- perf counters
-
senvcfg -
scontext -
mconfigptr -
mtinst -
mtval2 - Machine Configuration registers
- Machine Non-Maskable Interrupt Handling registers
- Machine Counter Setup registers
- Machine Debug/Trace registers
- Machine Dabug Mode registers
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with the unchecked CSR groups in the issue checklist and compare them with the RISC-V specification. No files, tests, or entry points are named in the issue, so repository exploration is required before implementation. Done means the listed Machine Configuration, Non-Maskable Interrupt Handling, Counter Setup, Debug/Trace, and Debug Mode registers are covered.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100