Multipin serial spi interface trait

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Assessment

Difficulty
5/5
Estimated time
Over a week
Newbie friendliness
25/100
Issue type
Feature
Clarity
Needs clarification
Activity status
Quiet
Tech stack
rust
Domain
embedded-iot

Research direction

Start by reviewing the existing standard SPI traits and the transaction details needed by quad, octospi, and Hyperbus peripherals. Compare those requirements with the proposed generic interface, then clarify whether Hyperbus belongs in the same abstraction. Done requires an agreed interface design rather than a narrowly scoped edit.

Written by the indexing model from the issue text.

Description

A lot of chips now support serial spi interfaces generally used for external memory like quad and octospi. There are also alternate protocols like Hyperbus that are defined on some supported peripherals, although it is not clear if that makes sense to support in a generic way here. The functionality doesn't fit strictly to the standard SPI traits, each transaction requiring more detail generally about the nature of each transaction. It may be helpful to define a standard interface for these types of peripherals. Opening a discussion about how best to support those types of buses.

Dominant language
Rust
Stars
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Forks
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