peripheral: "safer" API like the one svd2rust generates?

right now you can write any u32 in the peripherals' registers. This is bad because you may write 1s to reserved bits that are supposed to always be set to 0.

svd2rust generates a "safer" API that prevents this kind of problem. But it generates the API from SVD files and I don't if there are SVD files for these core peripherals.

Should we manually implement an API like that? Or, perhaps, should we be more conservative and just provide bit masks (as consts -- think const SCB_CPACR_CP10: u32 = 0b11 << 20) to begin with? (the bit masks would save you the trouble of having to look into the documentation for the right bit offset of each bit field but they are not fool proof as you can still write to reserved bits)

cc @thejpster

Start by reviewing the Cortex-M peripheral register APIs and the SCB_CPACR example mentioned in the issue, then compare the safety model generated by svd2rust. The issue does not name specific files or tests; done would require an agreed approach for preventing writes to reserved bits and corresponding implementation coverage.