cortex-m-rt: consider enabling divide by zero trap by default

In Cortex-M processors, (integer) divide by zero is not elevated to an exception/trap unless CCB->DIV_0_TRP is enabled, which is not the default setting. See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/configuration-and-control-register.

Instead, the result is undefined behavior/implementation defined. This is definitely surprising, if not unsound, under some expected behavior by Rust.

I'm not totally sure what happens on Cortex-M0/M0+ devices, or other devices without a hardware division unit.

We should probably set this bit in the cortex-m-rt init process (maybe toggled-off with an unsafe feature).

We might want to enable this to handle FFI or asm, but this is explicitly caught by Rust itself, rather than relying on the host to trap.

Start by investigating the cortex-m-rt init process and the Cortex-M differences mentioned in the issue, including devices without a hardware division unit. Determine whether DIV_0_TRP should be enabled by default and whether an unsafe opt-out is needed. Done means the supported-device behavior and default policy are established and verified.