rust-embedded / rust-embedded/cortex-m
Tracking issue for cache maintenance operations
Open
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- Dominant language
- Rust
- Stars
- 1k
- Forks
- 202
- Avg merge
- 6d 2h
- Merged PRs (30d)
- 2
Description
After #232 there are a few outstanding issues:
- Should any other (or all) cache maintenance operations be rewritten in assembly?
- This is necessary if the branch instructions inserted when calling DSB or ISB could cause UB
- Or if some other subtle condition we haven't noticed requires it
- Should any/all of the operations be static, instead of requiring an
&mut SCB?
Contributor guide
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reviewing the changes from #232 and the existing cache maintenance operations in the Cortex-M code. Investigate whether DSB or ISB branch instructions can cause undefined behavior and whether the operations should be static rather than requiring &mut SCB. Done means the open design questions are resolved and any agreed maintenance changes are implemented.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- embedded-iot
- Issue type
- Refactor
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100