Delay time influenced by memory configuration

How many cycles asm::delay() can be affected by how the chip memory is configured and even where the function ends up in Flash. The code assumes the loop takes 4 cycles and explains that interrupts may cause the function to delay longer than requested.

However, items such as Flash wait states, instruction cache, and function alignment can also cause the loop to take longer, even when interrupts are disabled. As an example, asm::delay() running on the NRF52840 can take 4, 5, or 6 cycles per loop depending on whether the function ends up 16, 8, or 2 byte aligned. This also means that the delay depends on how exactly the binary is compiled and linked.

This is very surprising behavior and I think a note to the above effect would be useful in the function's documentation. Perhaps the loop can be measured as part of initialization, but this would probably be unnecessary overhead.

Locate the Rust source and documentation for asm::delay, then read the existing explanation of its cycle count and interrupt behavior. Update the documentation to cover memory configuration, Flash wait states, instruction cache, and function alignment as additional causes of timing variation; done means the caveat is clearly documented.