Tracking Issue: Missing registers

Inspired by #71 this is an auto-generated tracker for the implementation state of all the AArch64 registers:

Key:

• REG -> register is present and all subfields are present
• REG (no child items) -> register is not present at all
• REG (has child items) -> register exists but is incomplete
• • SUB1-> this subitem exists
• • SUB2 -> this subitem is missing

Currently this only tracks the existence of a register or field, but it would also be useful to actually check the offset and width of each subfield as well. It also only recognises ConstantField and ConditionalField types, which might miss some fields.

import json
import os

names = []
regs = set()
with open("./Registers.json") as f:
    j = json.loads(f.read())
    for r in j:
        if r["_type"] != "Register" or r["state"] != "AArch64":
            continue
        
        name = r["name"].lower()
        if name[-4:] not in ["_el0", "_el1", "_el2", "_el3"]:
            continue
        mrs = [a for a in r["accessors"] if a["name"] == "A64.MRS"]
        msr = [a for a in r["accessors"] if a["name"] == "A64.MSRregister"]

        can_read = len(mrs) > 0
        can_write = len(msr) > 0


        kind = None
        if can_write and can_read:
            kind = "rw"
        elif can_write and not can_read:
            kind = "wo"
        elif not can_write and can_read:
            kind = "ro"

        enc = None
        if len(msr) > 0:
            enc = msr[0]["encoding"][0]["encodings"]
        if len(mrs) > 0:
            enc = mrs[0]["encoding"][0]["encodings"]

        if enc:
            crm = int(enc["CRm"]["value"].replace("'", ""), 2)
            crn = int(enc["CRn"]["value"].replace("'", ""), 2)
            op0 = int(enc["op0"]["value"].replace("'", ""), 2)
            op1 = int(enc["op1"]["value"].replace("'", ""), 2)
            op2 = int(enc["op2"]["value"].replace("'", ""), 2)
            enc = (crm, crn, op1, op2, op0)
        else:
            continue


        if name in regs:
            continue
        regs.add(name)
        
        subfields = []

        fs = r["fieldsets"]
        if len(fs) == 0:
            continue
        fs0 = fs[0]
        vals = fs0["values"]

        for v in vals:
            if v["_type"] == "Fields.Reserved":
                continue

            if v["_type"] == "Fields.Field":
                continue
            if v["_type"] == "Fields.ImplementationDefined":
                continue
            if v["_type"] == "Fields.Array":
                continue
            if v["_type"] == "Fields.Dynamic":
                continue
            if v["_type"] == "Fields.Vector":
                continue

            if v["_type"] == "Fields.ConstantField":
                name1 = v["name"]
                start = v["rangeset"][0]["start"]
                width = v["rangeset"][0]["width"]
                values = []
                if "constraints" in v["value"]:
                    xx = v["value"]["constraints"]
                    if xx is not None:
                        for val in xx["values"]:
                            if val["_type"] != "Values.Value":
                                continue
                            a = int(val["value"].replace("'", ""), 2)
                            values += [a]
            elif v["_type"] == "Fields.ConditionalField":
                cfs = [x for x in v["fields"] if x["field"]["_type"] == "Fields.ConstantField"]
                if len(cfs) == 0:
                    continue
                name1 = cfs[0]["field"]["name"]
                start = v["rangeset"][0]["start"]
                width = v["rangeset"][0]["width"]
                values = []
            else:
                exit(0)
                

            sf = {}
            sf["name"] = name1
            sf["start"] = start
            sf["width"] = width
            sf["values"] = values
            subfields += [sf]

        names += [(name, enc, kind, subfields)]

BASE_PATH = "/home/cub3d/projects/aarch64-cpu"

print("-"*32)
for (n, enc, kind, subfields) in names:

    pth = f"{BASE_PATH}/src/registers/{n}.rs"
    exists = os.path.exists(pth)

    if exists:
        with open(pth) as f:
            content = f.read()

        out = ""
        any_missing = False
        for s in subfields:
            name = s["name"]
            present = (name + " OFFSET") in content
            check = "x" if present else " "
            out += f"- - [{check}] {name}\n"
            if not present:
                any_missing = True

        if any_missing:
            print(f"- [ ] {n}")
            print(out.rstrip())
        else:
            print(f"- [x] {n}")
    else:
        print(f"- [ ] {n}")

Registers:

• accdata_el1
• actlr_el1
• actlr_el2
• actlr_el3
• actlrmask_el1
• actlrmask_el2
• afsr0_el1
• afsr0_el2
• afsr0_el3
• afsr1_el1
• afsr1_el2
• afsr1_el3
• aidr_el1
• amair2_el1
• amair2_el2
• amair2_el3
• amair_el1
• amair_el2
• amair_el3
• apdakeyhi_el1
• apdakeylo_el1
• apdbkeyhi_el1
• apdbkeylo_el1
• apgakeyhi_el1
• apgakeylo_el1
• apiakeyhi_el1
• apiakeylo_el1
• apibkeyhi_el1
• apibkeylo_el1
• ccsidr2_el1
• ccsidr_el1
• clidr_el1
• cntfrq_el0
• cnthctl_el2
• cnthp_ctl_el2
• cnthp_cval_el2
• cnthp_tval_el2
• cnthps_ctl_el2
• cnthps_cval_el2
• cnthps_tval_el2
• cnthv_ctl_el2
• cnthv_cval_el2
• cnthv_tval_el2
• cnthvs_ctl_el2
• cnthvs_cval_el2
• cnthvs_tval_el2
• cntkctl_el1
• cntp_ctl_el0
• cntp_cval_el0
• cntp_tval_el0
• cntpct_el0
• cntpctss_el0
• cntpoff_el2
• cntps_ctl_el1
• cntps_cval_el1
• cntps_tval_el1
• cntv_ctl_el0
• cntv_cval_el0
• cntv_tval_el0
• cntvct_el0
• cntvctss_el0
• cntvoff_el2
• contextidr_el1
• contextidr_el2
• cpacr_el1
• cpacrmask_el1
• cptr_el2
• cptr_el3
• cptrmask_el2
• csselr_el1
• ctr_el0
• dacr32_el2
• dbgauthstatus_el1
• dbgclaimclr_el1
• dbgclaimset_el1
• dbgdtr_el0
• dbgdtrrx_el0
• dbgdtrtx_el0
• dbgprcr_el1
• dbgvcr32_el2
• dczid_el0
• dlr_el0
• dpocr_el0
• dpotbr0_el1
• dpotbr0_el2
• dpotbr0_el3
• dpotbr1_el1
• dpotbr1_el2
• dspsr_el0
• elr_el1
• elr_el2
• elr_el3
• esr_el1
• esr_el2
• esr_el3
• far_el1
• far_el2
• far_el3
• fgwte3_el3
• fpexc32_el2
• gpcbw_el3
• gpccr_el3
• gptbr_el3
• hacdbsbr_el2
• hacdbscons_el2
• hacr_el2
• hafgrtr_el2
• hcr_el2
• hcrmask_el2
• hcrx_el2
• hcrxmask_el2
• hdbssbr_el2
• hdbssprod_el2
• hdfgrtr2_el2
• hdfgrtr_el2
• hdfgwtr2_el2
• hdfgwtr_el2
• hfgitr2_el2
• hfgitr_el2
• hfgrtr2_el2
• hfgrtr_el2
• hfgwtr2_el2
• hfgwtr_el2
• hpfar_el2
• hstr_el2
• icc_apr_el1
• icc_apr_el3
• icc_asgi1r_el1
• icc_bpr0_el1
• icc_bpr1_el1
• icc_cr0_el1
• icc_cr0_el3
• icc_ctlr_el1
• icc_ctlr_el3
• icc_dir_el1
• icc_domhppir_el3
• icc_eoir0_el1
• icc_eoir1_el1
• icc_hapr_el1
• icc_hppir0_el1
• icc_hppir1_el1
• icc_hppir_el1
• icc_hppir_el3
• icc_iaffidr_el1
• icc_iar0_el1
• icc_iar1_el1
• icc_icsr_el1
• icc_idr0_el1
• icc_igrpen0_el1
• icc_igrpen1_el1
• icc_igrpen1_el3
• icc_nmiar1_el1
• icc_pcr_el1
• icc_pcr_el3
• icc_pmr_el1
• icc_rpr_el1
• icc_sgi0r_el1
• icc_sgi1r_el1
• icc_sre_el1
• icc_sre_el2
• icc_sre_el3
• ich_apr_el2
• ich_contextr_el2
• ich_eisr_el2
• ich_elrsr_el2
• ich_hcr_el2
• ich_hfgitr_el2
• ich_hfgrtr_el2
• ich_hfgwtr_el2
• ich_hppir_el2
• ich_misr_el2
• ich_vctlr_el2
• ich_vmcr_el2
• ich_vtr_el2
• • PRIbits
• • PREbits
• • IDbits
• • SEIS
• • A3V
• • nV4
• • TDS
• • DVIM
• • ListRegs
• icv_apr_el1
• icv_bpr0_el1
• icv_bpr1_el1
• icv_cr0_el1
• icv_ctlr_el1
• icv_dir_el1
• icv_eoir0_el1
• icv_eoir1_el1
• icv_hapr_el1
• icv_hppir0_el1
• icv_hppir1_el1
• icv_hppir_el1
• icv_iar0_el1
• icv_iar1_el1
• icv_igrpen0_el1
• icv_igrpen1_el1
• icv_nmiar1_el1
• icv_pcr_el1
• icv_pmr_el1
• icv_rpr_el1
• id_aa64afr0_el1
• id_aa64afr1_el1
• id_aa64dfr0_el1
• • HPMN0
• • ExtTrcBuff
• • BRBE
• • MTPMU
• • TraceBuffer
• • TraceFilt
• • DoubleLock
• • PMSVer
• • CTX_CMPs
• • SEBEP
• • WRPs
• • PMSS
• • BRPs
• • PMUVer
• • TraceVer
• • DebugVer
• id_aa64dfr1_el1
• • ABL_CMPs
• • DPFZS
• • EBEP
• • ITE
• • ABLE
• • PMICNTR
• • SPMU
• • CTX_CMPs
• • WRPs
• • BRPs
• • SYSPMUID
• id_aa64dfr2_el1
• id_aa64fpfr0_el1
• id_aa64isar0_el1
• • RNDR
• • TLB
• • TS
• • FHM
• • DP
• • SM4
• • SM3
• • SHA3
• • RDM
• • Atomic
• • CRC32
• • SHA2
• • SHA1
• • AES
• id_aa64isar1_el1
• • LS64
• • XS
• • I8MM
• • DGH
• • BF16
• • SPECRES
• • SB
• • FRINTTS
• • GPI
• • GPA
• • LRCPC
• • FCMA
• • JSCVT
• • API
• • APA
• • DPB
• id_aa64isar2_el1
• id_aa64isar3_el1
• id_aa64mmfr0_el1
• • ECV
• • FGT
• • ExS
• • TGran4_2
• • TGran64_2
• • TGran16_2
• • TGran4
• • TGran64
• • TGran16
• • BigEndEL0
• • SNSMem
• • BigEnd
• • ASIDBits
• • PARange
• id_aa64mmfr1_el1
• • ECBHB
• • CMOW
• • TIDCP1
• • nTLBPA
• • AFP
• • HCX
• • ETS
• • TWED
• • XNX
• • SpecSEI
• • PAN
• • LO
• • HPDS
• • VH
• • VMIDBits
• • HAFDBS
• id_aa64mmfr2_el1
• id_aa64mmfr3_el1
• id_aa64mmfr4_el1
• id_aa64pfr0_el1
• • CSV3
• • CSV2
• • RME
• • DIT
• • AMU
• • MPAM
• • SEL2
• • SVE
• • RAS
• • GIC
• • AdvSIMD
• • FP
• • EL3
• • EL2
• • EL1
• • EL0
• id_aa64pfr1_el1
• • PFAR
• • DF2
• • MTEX
• • THE
• • GCS
• • MTE_frac
• • NMI
• • CSV2_frac
• • RNDR_trap
• • SME
• • MPAM_frac
• • RAS_frac
• • MTE
• • SSBS
• • BT
• id_aa64pfr2_el1
• id_afr0_el1
• id_dfr0_el1
• id_dfr1_el1
• id_isar0_el1
• id_isar1_el1
• id_isar2_el1
• id_isar3_el1
• id_isar4_el1
• id_isar5_el1
• id_isar6_el1
• id_mmfr0_el1
• id_mmfr1_el1
• id_mmfr2_el1
• id_mmfr3_el1
• id_mmfr4_el1
• id_mmfr5_el1
• id_pfr0_el1
• id_pfr1_el1
• id_pfr2_el1
• ifsr32_el2
• irtbrp_el1
• irtbrp_el2
• irtbrp_el3
• irtbru_el1
• irtbru_el2
• isr_el1
• ldstt_el1
• ldstt_el2
• lorc_el1
• lorea_el1
• lorid_el1
• lorn_el1
• lorsa_el1
• mair2_el1
• mair2_el2
• mair2_el3
• mair_el1
• mair_el2
• mair_el3
• mdccint_el1
• mdccsr_el0
• mdcr_el2
• mdcr_el3
• mdrar_el1
• mdscr_el1
• mdselr_el1
• mdstepop_el1
• mecid_a0_el2
• mecid_a1_el2
• mecid_p0_el2
• mecid_p1_el2
• mecid_rl_a_el3
• mecidr_el2
• mfar_el3
• midr_el1
• mpidr_el1
• mvfr0_el1
• mvfr1_el1
• mvfr2_el1
• nvhcr_el2
• nvhcrmask_el2
• nvhcrx_el2
• nvhcrxmask_el2
• osdlr_el1
• osdtrrx_el1
• osdtrtx_el1
• oseccr_el1
• oslar_el1
• oslsr_el1
• par_el1
• pfar_el1
• pfar_el2
• pir_el1
• pir_el2
• pir_el3
• pire0_el1
• pire0_el2
• pmccfiltr_el0
• pmccntr_el0
• pmccntsvr_el1
• pmceid0_el0
• pmceid1_el0
• pmcntenclr_el0
• pmcntenset_el0
• pmcr_el0
• pmecr_el1
• pmiar_el1
• pmicfiltr_el0
• pmicntr_el0
• pmicntsvr_el1
• pmintenclr_el1
• pmintenset_el1
• pmmir_el1
• pmovsclr_el0
• pmovsset_el0
• pmselr_el0
• pmsscr_el1
• pmswinc_el0
• pmuacr_el1
• pmuserenr_el0
• pmxevcntr_el0
• pmxevtyper_el0
• pmzr_el0
• por_el0
• por_el1
• por_el2
• por_el3
• rcwmask_el1
• rcwsmask_el1
• revidr_el1
• rmr_el1
• rmr_el2
• rmr_el3
• rvbar_el1
• • ResetAddress
• rvbar_el2
• • ResetAddress
• rvbar_el3
• • ResetAddress
• s2pir_el2
• s2por_el1
• scr2_el3
• scr_el3
• sctlr2_el1
• sctlr2_el2
• sctlr2_el3
• sctlr2mask_el1
• sctlr2mask_el2
• sctlr_el1
• sctlr_el2
• sctlr_el3
• sctlrmask_el1
• sctlrmask_el2
• scxtnum_el0
• scxtnum_el1
• scxtnum_el2
• scxtnum_el3
• sder32_el2
• sder32_el3
• smidr_el1
• smpri_el1
• smprimap_el2
• sp_el0
• sp_el1
• sp_el2
• spmaccessr_el1
• spmaccessr_el2
• spmaccessr_el3
• spmcfgr_el1
• spmcntenclr_el0
• spmcntenset_el0
• spmcr_el0
• spmdevaff_el1
• spmdevarch_el1
• spmiidr_el1
• spmintenclr_el1
• spmintenset_el1
• spmovsclr_el0
• spmovsset_el0
• spmrootcr_el3
• spmscr_el1
• spmselr_el0
• spmzr_el0
• spsr_el1
• spsr_el2
• spsr_el3
• stindex_el1
• stindex_el2
• stindex_el3
• tcr2_el1
• tcr2_el2
• tcr2mask_el1
• tcr2mask_el2
• tcr_el1
• tcr_el2
• tcr_el3
• tcrmask_el1
• tcrmask_el2
• tindex_el0
• tindex_el1
• tindex_el2
• tindex_el3
• tlbididr_el1
• tpidr2_el0
• tpidr3_el0
• tpidr3_el1
• tpidr3_el2
• tpidr3_el3
• tpidr_el0
• tpidr_el1
• tpidr_el2
• tpidr_el3
• tpidrro_el0
• tpmax0_el0
• tpmax0_el1
• tpmax0_el2
• tpmax1_el0
• tpmax1_el1
• tpmax1_el2
• tpmin0_el0
• tpmin0_el1
• tpmin0_el2
• tpmin1_el0
• tpmin1_el1
• tpmin1_el2
• trcitecr_el1
• trcitecr_el2
• trfcr_el1
• trfcr_el2
• ttbr0_el1
• ttbr0_el2
• ttbr0_el3
• ttbr1_el1
• ttbr1_el2
• tttbrp_el1
• tttbrp_el2
• tttbrp_el3
• tttbru_el1
• tttbru_el2
• vbar_el1
• vbar_el2
• vbar_el3
• vmecid_a_el2
• vmecid_p_el2
• vmpidr_el2
• vnccr_el2
• vncr_el2
• vpidr_el2
• vstcr_el2
• vsttbr_el2
• vtcr_el2
• vttbr_el2
• amcfgr_el0
• amcg1idr_el0
• amcgcr_el0
• amcntenclr0_el0
• amcntenclr1_el0
• amcntenset0_el0
• amcntenset1_el0
• amcr_el0
• amuserenr_el0
• brbcr_el1
• brbcr_el2
• brbfcr_el1
• brbidr0_el1
• brbinfinj_el1
• brbsrcinj_el1
• brbtgtinj_el1
• brbts_el1
• gcscr_el1
• gcscr_el2
• gcscr_el3
• gcscre0_el1
• gcspr_el0
• gcspr_el1
• gcspr_el2
• gcspr_el3
• mpam0_el1
• mpam1_el1
• mpam2_el2
• mpam3_el3
• mpambw0_el1
• mpambw1_el1
• mpambw2_el2
• mpambw3_el3
• mpambwcap_el2
• mpambwidr_el1
• mpambwsm_el1
• mpamctl_el1
• mpamctl_el2
• mpamctl_el3
• mpamhcr_el2
• mpamidr_el1
• mpamsm_el1
• mpamvidcr_el2
• mpamvidsr_el2
• mpamvidsr_el3
• mpamvpm0_el2
• mpamvpm1_el2
• mpamvpm2_el2
• mpamvpm3_el2
• mpamvpm4_el2
• mpamvpm5_el2
• mpamvpm6_el2
• mpamvpm7_el2
• mpamvpmv_el2
• gcr_el1
• gmid_el1
• rgsr_el1
• tfsr_el1
• tfsr_el2
• tfsr_el3
• tfsre0_el1
• disr_el1
• erridr_el1
• errselr_el1
• erxaddr_el1
• erxctlr_el1
• erxfr_el1
• erxgsr_el1
• erxmisc0_el1
• erxmisc1_el1
• erxmisc2_el1
• erxmisc3_el1
• erxpfgcdn_el1
• erxpfgctl_el1
• erxpfgf_el1
• erxstatus_el1
• vdisr_el2
• vdisr_el3
• vsesr_el2
• vsesr_el3
• id_aa64smfr0_el1
• smcr_el1
• smcr_el2
• smcr_el3
• pmbidr_el1
• pmblimitr_el1
• pmbmar_el1
• pmbptr_el1
• pmbsr_el1
• pmbsr_el2
• pmbsr_el3
• pmscr_el1
• pmscr_el2
• pmsdsfr_el1
• pmsevfr_el1
• pmsfcr_el1
• pmsicr_el1
• pmsidr_el1
• pmsirr_el1
• pmslatfr_el1
• pmsnevfr_el1
• id_aa64zfr0_el1
• zcr_el1
• zcr_el2
• zcr_el3
• trbbaser_el1
• trbidr_el1
• trblimitr_el1
• trbmar_el1
• trbmpam_el1
• trbptr_el1
• trbsr_el1
• trbsr_el2
• trbsr_el3
• trbtrg_el1

Start with Registers.json and the generator shown in the issue, then inspect the corresponding src/registers/*.rs files for unchecked entries. Done means implementing the missing AArch64 registers and fields and updating the tracker; the issue does not name a narrower subset or tests.