rust-embedded / rust-embedded/aarch64-cpu
Many missing register fields (and RES1 handling query)
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- Dominant language
- Rust
- Stars
- 116
- Forks
- 38
- PR merge metrics
- No merged PRs in 30d
Description
SCTLR_EL1::SPAN minimally is missing, which is necessary for implementation of a trusted OS at S-EL1.
However, looking closer, it seems all positions between bits 20 and 23 are missing. So: SPAN, EIS, IESB, TSCXT. I'm guessing the story is the same for the other ELx versions of this register.
In the longer term, it would be great to see register definitions be derived automatically from Arm's published machine-readable specification packages (the "SysReg" MRS package).
Also, I couldn't seem to see the RES1 fields handled anywhere, e.g. for TCR_EL1, so I had to hardcode those manually. It would be good if the Writeable trait impl managed that for you.
Contributor guide
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the SCTLR_EL1 and TCR_EL1 register definitions and compare the documented bit ranges, especially SCTLR_EL1 bits 20–23 and RES1 fields. Check whether the other ELx SCTLR registers have the same omissions and how the Writeable trait currently handles writes. Done means the requested register fields and RES1 behavior are represented consistently.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- operating-systems
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100