rust-embedded / rust-embedded/aarch32
Should `aarch32_cpu::cache` functions issue proper memory/instruction barriers?
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- Dominant language
- Rust
- Stars
- 66
- Forks
- 25
- Avg merge
- 4d 6h
- Merged PRs (30d)
- 4
Description
Cache operations require dsb/isb to properly take effect. dsb is needed because pending cache operations are asynchronous and need time to complete. isb is (sometimes) needed to flush the pipeline in the event that it contains a stale instruction.
Currently, the utility functions in aarch32_cpu::cache do not issue these barriers, so an asm!("dsb", "isb") is required in order for them to perform what they claim. Should these functions be updated to include dsb/isb? Compiler fences might also be good as a sanity check (e.g. cortex_m issues compiler_fence(Ordering::SeqCst) before every dsb()/isb() call)
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Research direction
Start at the utility functions under aarch32_cpu::cache and inspect their callers to understand the current barrier expectations. Compare the stated dsb/isb and compiler-fence requirements with the approach used by cortex_m. Done means the cache helpers provide the required ordering and completion behavior without callers needing separate inline assembly, with affected paths validated.
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Assessment
- Tech stack
- rust
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Active
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100