rust-embedded / rust-embedded/aarch32
Dynamically discover cache size
Nobody has claimed this yet.
- Dominant language
- Rust
- Stars
- 66
- Forks
- 25
- Avg merge
- 4d 6h
- Merged PRs (30d)
- 4
Description
Currently the cache APIs require the cache layout to be known at compile time.
We could read CSSIDR and compute them dynamically, saving the user a bunch of work.
See https://github.com/leeeastwood/Haiway/blob/153b6861f864966c454f97febe03ae191a9a8657/app/kernel-example/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_cache.c#L396 as an example of this approach.
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the cache APIs and the code that currently requires the cache layout at compile time. Read the referenced alt_cache.c example and investigate how CSSIDR can provide the cache layout dynamically; done means the APIs discover the cache size without requiring users to specify it.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 48/100