Issue: Unrecognized opcode addw when building for RV32 with Zalrsc

Hello,
I am experiencing an error when building with 32-bit compiler using LR/SC extension. According to the platform requirements documentation, I can skip Zaamo extension and use Zalrsc. On 32-bit environment, using this command:

make PLATFORM=generic PLATFORM_RISCV_XLEN=32 CROSS_COMPILE=riscv32-unknown-linux-gnu- PLATFORM_RISCV_ISA=rv32imc_zalrsc

I get the following error:

/tmp/opensbi/lib/sbi/riscv_atomic.c: Assembler messages:
/tmp/opensbi/lib/sbi/riscv_atomic.c:51: Error: unrecognized opcode `addw a4,a5,a1'
/tmp/opensbi/lib/sbi/riscv_atomic.c:51: Error: unrecognized opcode `addw a3,a4,a5'

The error is correct because, according to RISCV documentation (Instruct Set Manual) pages 42-43:

Most integer computational instructions operate on XLEN-bit values. Additional instruction variants are
provided to manipulate 32-bit values in RV64I, indicated by a 'W' suffix to the opcode. These "*W"
instructions ignore the upper 32 bits of their inputs and always produce 32-bit signed values, sign-
extending them to 64 bits, i.e. bits XLEN-1 through 31 are equal.

ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB but
operate on 32-bit values and produce signed 32-bit results.

So addw should not appear on 32-bit. The error appears to be in this function:

#elif __riscv_zalrsc
  long ret, temp;
#if __SIZEOF_LONG__ == 4
  __asm__ __volatile__("1:lr.w.aqrl  %1,%0\n"
           "  addw  %2,%1,%3\n"
           "  sc.w.aqrl  %2,%2,%0\n"
           "  bnez  %2,1b"
           : "+A"(atom->counter), "=&r"(ret), "=&r"(temp)
           : "r"(value)
           : "memory");
#elif __SIZEOF_LONG__ == 8
  __asm__ __volatile__("1:lr.d.aqrl  %1,%0\n"
           "  add  %2,%1,%3\n"
           "  sc.d.aqrl  %2,%2,%0\n"
           "  bnez  %2,1b"
           : "+A"(atom->counter), "=&r"(ret), "=&r"(temp)
           : "r"(value)
           : "memory");

Am I missing something?

Inspect lib/sbi/riscv_atomic.c around line 51, focusing on the SIZEOF_LONG == 4 branch of the Zalrsc implementation and its inline assembly. Re-run the supplied RV32 build command and confirm the build completes without an unrecognized addw opcode.