riscv-software-src / riscv-software-src/opensbi
CSR_MHPMCOUNTER3 counter initialization on hart_pmu_get_allowed_bits()
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- Dominant language
- C
- Stars
- 1.5k
- Forks
- 712
- PR merge metrics
- No merged PRs in 30d
Description
I'm working on expanding the functionality of the RISC-V HPM and during my testing I stumbled upon a "bug" where the value of CSR_MHPMCOUNTER3 as all it's bits set to 1 during the openSBI initialization process. Should it not respect the value defined by the architecture during an HW reset? Or is there any reason why leaving the value as is advantageous?
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start at hart_pmu_get_allowed_bits() and trace how CSR_MHPMCOUNTER3 is initialized during OpenSBI startup. Compare that behavior with the RISC-V architecture's hardware-reset requirements; done means establishing whether the value is compliant and, if not, identifying the required initialization change.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- c
- Domain
- operating-systems
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100