riscv-software-src / riscv-software-src/opensbi
Why is MTIME M-mode only?
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Description
Since commit 59a08cd7d632bb2394a29956497dfe7829099997, which is part of Split region permissions into M-mode and SU-mode MTIME is M-mode only.
This breaks OSes that read MTIME directly to avoid the overhead of emulated rdtime instructions on hardware that don't have native support for the instruction. The emulated rdtime has huge overhead. MTIME is well defined by the RISC-V standard, so we thought we could rely on it.
Is MTIME off-limits for OS code now, and why? Is that documented somewhere? Could read-only access to the CLINT/MTIME memory region be added back so low overhead timer reads are possible again on all RISC-V platforms?
Please advise how we should proceed.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Review commit 59a08cd7d632bb2394a29997dfe7829099997 and the linked discussion about splitting region permissions, then trace the current CLINT/MTIME access policy. Compare it with the RISC-V standard and the reported rdtime overhead; done means the policy is clarified or an agreed read-only access change is implemented and validated.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, operating-systems
- Issue type
- Bug
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100