riscv-software-src / riscv-software-src/opensbi
Smp Linux hardware support for dual core
Open
Nobody has claimed this yet.
- Dominant language
- C
- Stars
- 1.5k
- Forks
- 712
- PR merge metrics
- No merged PRs in 30d
Description
We have designed single core and planning to extend it to dual core and boot smp Linux(both core are identical). We have found out that we need following things to be implemented correctly.
- Cache coherence
- Atomic instruction to be implemented for dual core
- Inter processor interrupts(use aclint for that)
- Memory barrier synchronisation instruction (fence, fence.i)
Apart from that do anything else need to be considered to make dual core smp Linux compatible. We are building smp Linux using buildroot tools.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reviewing the existing single-core OpenSBI support and the dual-core Linux boot path built with Buildroot. The issue names cache coherence, atomic instructions, ACLINT inter-processor interrupts, and fence/fence.i synchronization; done means dual-core SMP Linux boots correctly with these requirements and any additional compatibility gaps identified.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- c, linux
- Domain
- embedded-iot, operating-systems
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100