riscv-software-src / riscv-software-src/opensbi
what if RISC-V CPU has no member mtime_addr in aclint_mtimer_data
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- Dominant language
- C
- Stars
- 1.5k
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- 712
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Description
For T-Head RSICV CPU C910, it read mtimer value via csr like following:
__ASM volatile("csrr %0, 0xc01" : "=r"(result));
Actually, It has no memory map for mtimer counter value . In this case how to implement aclint function? make mtimer_time_rd32 as a weak function and re-write it in platform?
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reading the ACLINT timer implementation around aclint_mtimer_data and mtimer_time_rd32, then compare it with the C910's CSR-based mtime access described in the issue. Done means the platform-specific timer access approach is defined and the ACLINT function no longer assumes a memory-mapped mtime counter for this case.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- c
- Domain
- embedded-iot, operating-systems
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 32/100