riscv-software-src / riscv-software-src/opensbi

OpenSBI service in HSS hangs

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C
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Description

Hello,
I am trying to boot Linux using https://github.com/polarfire-soc/polarfire-soc-buildroot-sdk repository. What I want to change is the boot address. I would like to boot Linux from DDR connected to the process via FPGA. The address of this DDR is 0x20_0000_0000. I think I have changed it everywhere I had to.
I am aware that it may be not exactly the right place to ask this question but I think that it hangs in the openSBI service in the HSS, where it should start U-boot. I have added some prints and it looks like that:

[11.172343] HSS_Boot_PMPSetupHandler(): Hart1 setup complete
HSS_OpenSBI_IPIHandler(): fw_size 1c214
HSS_OpenSBI_IPIHandler(): hss_start 20220000 1c214 
HSS_OpenSBI_IPIHandler(): p_extended_buffer 2030000028 
HSS_OpenSBI_Setup(): MTVEC switching from 20220230 to 20220100

I also had once the error like that:
sbi_emulate_csr_read: hartid1: invalid csr_num=0x42

I am looking for some advice how to debug it and find the source of the problem.

Regards
WL

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  3. Fork the repository and make your change on a branch.
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Research direction

Start with the reported HSS_OpenSBI_IPIHandler() and HSS_OpenSBI_Setup() log points, then inspect the sbi_emulate_csr_read error for the failing CSR access. Reproduce the hang while booting Linux from DDR at 0x20_0000_0000 and trace whether control reaches U-Boot. Done means identifying the source of the OpenSBI hang or documenting the specific failing handoff.

Written by the indexing model from the issue text.

Assessment

Tech stack
c
Domain
embedded-iot, operating-systems
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

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