Cache chip specs
Nobody has claimed this yet.
- Dominant language
- Rust
- Stars
- 1
- Forks
- 0
- Avg merge
- 18m
- Merged PRs (30d)
- 1
Description
Deserializing a chip spec from JSON is slow in quilc (on the order of 1s for an Aspen-M-3 chip). In quilc, we got around that by adding a chip cache, so that only the first use of the chip was slow. We ought to include the same to alleviate that slow deserialization.
Alternatively, we could:
- make use of the caching already in quilc
- improve performance in quilc
The former is reasonable, but would be gated by review from quil-lang; if we instead implement it here, we can move quicker. The latter alternative is not a sure-thing and would take a good amount of effort. So I think managing the cache ourselves is the best option.
Contributor guide
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the chip-spec JSON deserialization entry point in libquil-sys and compare it with the existing chip cache in quilc. Confirm how chip specs are reused and define completion as avoiding repeated slow deserialization while preserving the current chip-spec behavior; no specific file or test is named in the issue.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- tooling
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100