Documentation: need for memory barriers

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documentation pio question

I think the documentation could use some extra information about the need for memory barriers: so far as I can see, there's currently neither explanatory material in the SDK, nor the raw information in the datasheet to figure it out for yourself.

As an example, I just got caught out where I had an interrupt handler for the PIO Tx FIFO, which looped loading bytes into the FIFO until the interrupt status (IRQ0_INTS) cleared - this overflowed the FIFO because the status read apparently overtook the FIFO write. Evidently there's a write buffer in there somewhere. Easily cured with a DMB instruction, but I couldn't find this write buffer documented anywhere.

Also, there's the mysterious __mem_fence_acquire() where the SDK documentation seems to assume you know what it does, and drilling down into the SDK source suggests it's just a compatibility veneer for a facility defined elsewhere - yet Google doesn't give any hits apart from the Pico SDK itself.

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