bcm2711 PCIe Interrupt Pins B through D not functional
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Assessment
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Newbie friendliness
- 35/100
- Issue type
- Bug
- Clarity
- Clearly specified
- Activity status
- Stale
- Tech stack
- linux
- Domain
- embedded-iot, operating-systems
Research direction
Start with arch/arm/boot/dts/bcm2711.dtsi and compare its PCIe interrupt map with the attached bcm2711-pcie-int.zip change, particularly the entries for pins B through E. Validate the map on a Raspberry Pi Compute Module 4 with PCIe peripherals using those pins, and confirm that MSI behavior remains unaffected.
Written by the indexing model from the issue text.
Description
This pertains to Linux for the Raspberry Pi version 5.10.74 and the
included Device Tree definition files. The file
"arch/arm/boot/dts/bcm2711.dtsi" only defines an interrupt for PCIe
interrupt Pin A. Devices that use interrupt Pins C, D, or E will not
function properly because they cannot request interrupts.
Existing definition of interrupt map for PCIe in "bcm2711.dtsi":
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
IRQ_TYPE_LEVEL_HIGH>;
The work around or correction to the interrupt map is this:
interrupt-map-mask = <0x0 0x0 0x0 0xFF>;
interrupt-map =
<0 0 0 1
&gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2
&gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3
&gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4
&gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
I tested this change on the Raspberry Pi Compute Module 4 and
associated IO board. There is not enough documentation for the
interrupt controllers in the BCM2711 for me to verify that the
assigned interrupt request numbers are valid. The pins do have to use
different interrupt request numbers, or the associated interrupt
handler is not called.
This problem affects any PCIe peripherals or bus multiplexers that use
interrupt Pins C through E, either directly or indirectly due to
interrupt "swizzling" (rotation). The problem does not affect the
operation of Message Signaled Interrupts (MSI) on the PCIe interface
because they use a different set of interrupt request lines.
A modified "bcm2711.dtsi" is attached. Search for initials "EWW".
- Dominant language
- C
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