SPI Driver: Long CSB-SCK delay and SCK-CSB delay leads to poor performance of SPI
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Assessment
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Newbie friendliness
- 25/100
- Issue type
- Bug
- Clarity
- Needs clarification
- Activity status
- Stale
- Tech stack
- c, linux
- Domain
- embedded-iot, performance
Research direction
Start from the spidev interface and reproduce the transfer while probing CSB, SCK, SDI, and SDO as described. Measure the delays before the first clock and after the last clock, then identify the kernel SPI path responsible; done means documenting or correcting the delays and confirming improved transfer performance.
Written by the indexing model from the issue text.
Description
Hi, I'm when I use the spidev interface with my code. I probed the waveform for the 4 pins, CSB, SCK, SDI and SDO. However I noticed when I set the spi max speed to higher frequency SCK, but overall performance does not imporve a lot. So I went on to investigate this issue by probing the 4 pins using oscilloscope.
Surprisingly, I noticed there is a measurable time between CS selection and the first SPI clock and again a delay between the last SPI clock and CS deselected. This huge delay between CS goes LOW and first SPI clock begin is causing my overall SPI transfer to be very slow. Is there any modifications that I can do for this issue?
I really need help to optimize the SPI performance and will really appreciate any help or guidance given. Thanks in advance.
- Dominant language
- C
- Stars
- 13.2k
- Forks
- 5.5k
- Avg merge
- 2d 21h
- Merged PRs (30d)
- 21
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