[qnn] about the new arch chipset and larger models
Nobody has claimed this yet.
- Dominant language
- Python
- Stars
- 5k
- Forks
- 1.2k
- Avg merge
- 2d 10h
- Merged PRs (30d)
- 581
Description
Hi Teams,
forgive me about "too noisy" with so many issues. For I am so excited with the activate community with edge deployment with qualcomm chips.
I found some code about 8397/8797 with multiple NPUs with 320 tops (320 tops int8 dense). So we can image that larger models used in the chipset.
So I have some questions about it:
-
To speed up the prefill, can we use two/or more npu in the prefill stage, like tensor parallelism on GPU? If it can be achieved, how to?
-
about the MOE models (low computation, lower bandwith, powerful), can we use moe model with executorch/qnn sdk?
-
lora/multi lora support
-
SSD for larger models
Looking forward to you insights.
cc @cccclai @cbilgin @abhinaykukkadapu @winskuo-quic @shewu-quic @haowhsu-quic @DannyYuyang-quic
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
No files or tests are named. Start by reviewing ExecuTorch’s QNN SDK integration and its documented support for multi-NPU prefill, MoE models, LoRA, and SSD-backed model storage; the issue needs to be narrowed into a scoped capability or implementation task before work can be considered done.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- machine-learning
- Domain
- embedded-iot, machine-learning
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100