Windows: SMT halves L1i/L1d/L2 cache instance count (cache.processor_count doubled)

On AMD Ryzen CPUs with SMT , cpuinfo_get_l1i_caches_count() / cpuinfo_get_l1d_caches_count() / cpuinfo_get_l2_caches_count() return half the expected number of cache instances on Windows, with each instance's processor_count doubled. the single core cache size comes out correct.
I also tested on an Intel CPU, though without hyper-threading and the total cache sizes came out correct.

Environment:

cpuinfo: main branch, fetched via CMake FetchContent, rebuilt today
Compiler: GCC/GNU 15.2.0 (MinGW-w64)
OS: Windows 11, fully updated (same binary tested across all three machines)

I tested this in three different devices

1st device:
CPU: AMD Ryzen 7 260 (8 cores / 16 threads)

results:

name: AMD Ryzen 7 260
ARCH: x86_64 (64-bit)
physical cores: 8
Logical threads: 16

l1i single core: 32 KB
l1d single core: 32 KB
l2 single core: 1024 KB

L1i[0] size=32768 processor_start=0 processor_count=4
L1i[1] size=32768 processor_start=4 processor_count=4
L1i[2] size=32768 processor_start=8 processor_count=4
L1i[3] size=32768 processor_start=12 processor_count=4

l1 cache total: 256 KB
l2 cache total: 4096 KB
l3 cache total: 16384 KB
l4 cache total: NaN

2nd device:
CPU: AMD Ryzen 3 5300U (4 cores / 8 threads)

results:

name: AMD Ryzen 3 5300U
ARCH: x86_64 (64-bit)
physical cores: 4
Logical threads: 8

l1i single core: 32 KB
l1d single core: 32 KB
l2 single core: 512 KB

L1i[0] size=32768 processor_start=0 processor_count=4
L1i[1] size=32768 processor_start=4 processor_count=4

l1 cache total: 128 KB
l2 cache total: 1024 KB
l3 cache total: 4096 KB
l4 cache total: NaN

3rd device (correct output):
CPU: Intel Core i7-9700K (8 cores / 8 threads)

results:

name: Intel Core i7-9700K
ARCH: x86_64 (64-bit)
physical cores: 8
Logical threads: 8

l1i single core: 32 KB
l1d single core: 32 KB
l2 single core: 256 KB

L1i[0] size=32768 processor_start=0 processor_count=1
L1i[1] size=32768 processor_start=1 processor_count=1
L1i[2] size=32768 processor_start=2 processor_count=1
L1i[3] size=32768 processor_start=3 processor_count=1
L1i[4] size=32768 processor_start=4 processor_count=1
L1i[5] size=32768 processor_start=5 processor_count=1
L1i[6] size=32768 processor_start=6 processor_count=1
L1i[7] size=32768 processor_start=7 processor_count=1

l1 cache total: 512 KB
l2 cache total: 2048 KB
l3 cache total: 12288 KB
l4 cache total: NaN

bug.cpp

Start by building and running the attached bug.cpp on the reported Windows SMT systems, then trace the Windows cache enumeration path in the repository. Done means L1i, L1d, and L2 instance counts and processor_count values are correct on the AMD examples while the reported Intel behavior remains correct.