Invalid RAM address parsed from CMSIS pack for STM32U073 MCU

Hello!

I am trying to establish RTT comms with STM32U073 MCU. The CMSIS pack version is Keil.STM32U0xx_DFP@2.1.0.
RAM start is reported as 0x20002000, but should be 0x20000000.

With https://github.com/pyocd/pyOCD/pull/1868 I get:

$ pyocd rtt --target stm32u073ccux                                                                                      
0002681 W Overlapping memory regions in file /home/robert/.local/share/cmsis-pack-manager/Keil/STM32U0xx_DFP/2.1.0.pack 
(STM32U073K8Ux); deleting outer region. Further warnings will be suppressed for this file. [cmsis_pack]                 
0002791 I Target type is stm32u073ccux [board]                                                                          
0003233 I DP IDR = 0x6ba02477 (v2 rev6) [dap]
0003251 I debugvar 'DbgMCU_APB1FZR' = 0xc0001833 (3221231667) [pack_target]
0003251 I debugvar 'DbgMCU_APB2FZR' = 0x70800 (460800) [pack_target]
0003251 I debugvar 'DbgMCU_CR' = 0x6 (6) [pack_target]
0003312 I AHB-AP#0 IDR = 0x84770001 (AHB-AP var0 rev8) [discovery]
0003317 I APB-AP#1 IDR = 0x54770002 (APB-AP var0 rev5) [discovery]
0003322 I AHB-AP#0 Class 0x1 ROM table #0 @ 0xf0000000 (designer=020:ST part=489) [rom_table]
0003326 I [0]<e00ff000:ROM class=1 designer=43b:Arm part=4c0> [rom_table]
0003326 I   AHB-AP#0 Class 0x1 ROM table #1 @ 0xe00ff000 (designer=43b:Arm part=4c0) [rom_table]
0003331 I   [0]<e000e000:SCS v6-M class=14 designer=43b:Arm part=008> [rom_table]
0003333 I   [1]<e0001000:DWT v6-M class=14 designer=43b:Arm part=00a> [rom_table]
0003335 I   [2]<e0002000:BPU v6-M class=14 designer=43b:Arm part=00b> [rom_table]
0003338 I APB-AP#1 Class 0x1 ROM table #0 @ 0xf0000000 (designer=020:ST part=000) [rom_table]
0003342 I [0]<f0001000:DBGMCU class=15 designer=020:ST part=000> [rom_table]
0003352 I CPU core #0: Cortex-M0+ r0p1, v6.0-M architecture [cortex_m]
0003352 I   Extensions: [MPU] [cortex_m]
0003353 I Setting core #0 (Cortex-M0+) default reset sequence to ResetSystem [pack_target]
0003355 I 2 hardware watchpoints [dwt]
0003357 I 4 hardware breakpoints, 0 literal comparators [fpb]
Memory map:


<MemoryMap@0x70ebf5453cb0 regions=[<FlashRegion@0x70ebe659e170 name=Flash type=MemoryType.FLASH start=0x8000000 end=0x80
3ffff length=0x40000 access=rx blocksize=0x800>, <RamRegion@0x70ebe6416dd0 name=SRAM2 type=MemoryType.RAM start=0x200020
00 end=0x20003fff length=0x2000 access=rwx>]>
Total search size: 8192
addr: 0x20002000, read_size: 32                                                                                         
addr: 0x20002020, read_size: 32                                                                                         
addr: 0x20002040, read_size: 32

...

addr: 0x20003fc0, read_size: 32                                                                                         
addr: 0x20003fe0, read_size: 32                                                                                         
0008810 C Control block not found [__main__] 

If I specify address and search size manually, RTT CB is found:

$ pyocd rtt --target stm32u073ccux -a 0x20000000 -s 0x1000                                                              
0002724 W Overlapping memory regions in file /home/robert/.local/share/cmsis-pack-manager/Keil/STM32U0xx_DFP/2.1.0.pack 
(STM32U073K8Ux); deleting outer region. Further warnings will be suppressed for this file. [cmsis_pack]                 
0002844 I Target type is stm32u073ccux [board]                                                                          
0003311 I DP IDR = 0x6ba02477 (v2 rev6) [dap]                                                                           
0003346 I debugvar 'DbgMCU_APB1FZR' = 0xc0001833 (3221231667) [pack_target]                                             
0003346 I debugvar 'DbgMCU_APB2FZR' = 0x70800 (460800) [pack_target]                                                    
0003346 I debugvar 'DbgMCU_CR' = 0x6 (6) [pack_target]                                                                  
0003361 I AHB-AP#0 IDR = 0x84770001 (AHB-AP var0 rev8) [discovery]                                                      
0003367 I APB-AP#1 IDR = 0x54770002 (APB-AP var0 rev5) [discovery]                                                      
0003372 I AHB-AP#0 Class 0x1 ROM table #0 @ 0xf0000000 (designer=020:ST part=489) [rom_table]                           
0003376 I [0]<e00ff000:ROM class=1 designer=43b:Arm part=4c0> [rom_table]
0003376 I   AHB-AP#0 Class 0x1 ROM table #1 @ 0xe00ff000 (designer=43b:Arm part=4c0) [rom_table]
0003381 I   [0]<e000e000:SCS v6-M class=14 designer=43b:Arm part=008> [rom_table]
0003383 I   [1]<e0001000:DWT v6-M class=14 designer=43b:Arm part=00a> [rom_table]
0003386 I   [2]<e0002000:BPU v6-M class=14 designer=43b:Arm part=00b> [rom_table]
0003389 I APB-AP#1 Class 0x1 ROM table #0 @ 0xf0000000 (designer=020:ST part=000) [rom_table]
0003393 I [0]<f0001000:DBGMCU class=15 designer=020:ST part=000> [rom_table]
0003403 I CPU core #0: Cortex-M0+ r0p1, v6.0-M architecture [cortex_m]
0003404 I   Extensions: [MPU] [cortex_m]
0003404 I Setting core #0 (Cortex-M0+) default reset sequence to ResetSystem [pack_target]
0003406 I 2 hardware watchpoints [dwt]
0003408 I 4 hardware breakpoints, 0 literal comparators [fpb]
Total search size: 4096
addr: 0x20000000, read_size: 32
addr: 0x20000020, read_size: 32
addr: 0x20000040, read_size: 32
addr: 0x20000060, read_size: 32

...

addr: 0x20000f80, read_size: 32
addr: 0x20000fa0, read_size: 32
0003645 I 1 up channels and 1 down channels found [rtt_cmd]
0003645 I Reading from up channel 0 ("Terminal") [rtt_cmd]
0003648 I Writing to down channel 0 ("Terminal") [rtt_cmd]

Start with the pyocd rtt entry point and the CMSIS pack memory-map parsing path. Compare the STM32U073 pack's RAM regions with the reported memory map and the manual RTT search results. Done means the automatic search uses 0x20000000 and finds the RTT control block for this target.