Reads via gdb are not marked as cacheable

It appears that when I perform a memory read [edit: on a Cortex-M7, STM32H750] through gdb and pyocd gdb, what I get is the actual contents of the backing SRAM, not the view as seen by the CPU - which means that if the D-cache is enabled and I'm reading something in cacheable memory that hasn't been cleaned from the cache, I won't get the right results. This leads to some confusing behavior:

# Random data in AXI SRAM after boot
(gdb) x/16w 0x24020000
0x24020000:	-1760592895	1630186032	89348259	1028313498
0x24020010:	-1061064142	99499594	1160210010	-1502964292
0x24020020:	89785445	-1251708343	-1768125164	-1424349768
0x24020030:	1224770264	-897671144	1670031863	1483403987
# Use the CPU to memset it
(gdb) call memset((void*)0x24020000, 0, 32)
$1 = (void *) 0x24020000
# Result of memset is not visible
(gdb) x/16w 0x24020000
0x24020000:	-1760592895	1630186032	89348259	1028313498
0x24020010:	-1061064142	99499594	1160210010	-1502964292
0x24020020:	89785445	-1251708343	-1768125164	-1424349768
0x24020030:	1224770264	-897671144	1670031863	1483403987
# But if memset is immediately followed by a cache clean...
(gdb) call memset((void*)0x24020000, 0, 32)
$2 = (void *) 0x24020000
(gdb) set SCB->DCCMVAC = 0x24020000
(gdb) x/16w 0x24020000
0x24020000:	0	0	0	0
0x24020010:	0	0	0	0
0x24020020:	89785445	-1251708343	-1768125164	-1424349768
0x24020030:	1224770264	-897671144	1670031863	1483403987

Once again I'm not sure what the right fix here is. :( It looks like the AHB-AP allows setting e.g. HPROT_CACHEABLE, but it seems like what we actually want for gdb is to use whichever cacheability settings the CPU would apply, as configured through the MPU if applicable, right?

Start by tracing the pyocd gdb memory-read path and how its AHB-AP transfers configure HPROT_CACHEABLE. Compare that behavior with the Cortex-M7 MPU cacheability settings described in the report, then define and validate what a GDB read should return when data remains in the CPU cache.