SystemVerilog-style slices of arbitrary base
Open
Nobody has claimed this yet.
enhancement
good first issue
Language Design
- Dominant language
- Rust
- Stars
- 126
- Forks
- 6
- PR merge metrics
- No merged PRs in 30d
Description
This issue has no description.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue body names no files, tests, or entry points. Start by locating the compiler's existing slice syntax handling and compare it with SystemVerilog-style slices of arbitrary base; define the expected syntax and behavior, then add tests that establish when the feature is complete.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100