pc2 / pc2/sus-compiler

Explicit latency annotations on Values?

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enhancement Language Design
Dominant language
Rust
Stars
126
Forks
6
PR merge metrics
No merged PRs in 30d

Description

In the example:

// Recursive Tree Add module recurses smaller copies of itself. 
module TreeAdder #(int WIDTH) {
	interface TreeAdder : int[WIDTH] values'0 -> int total

	if WIDTH == 0 {
		// Have to explicitly give zero a latency count. 
		// Otherwise total's latency can't be determined. 
		int zero'0 = 0
		total = zero
	} else if WIDTH == 1 {
		total = values[0]
	} else {
		gen int L_SZ = WIDTH / 2
		gen int R_SZ = WIDTH - L_SZ

		int[L_SZ] left_part, int[R_SZ] right_part = SplitAt(values)

		int left_total = TreeAdder(left_part)
		int right_total = TreeAdder(right_part)
		
		// Can add pipelining registers here too. 
		// Latency Counting will figure it out.
		reg total = left_total + right_total
	}
}

We use int zero'0 = 0 because otherwise the LC system can't figure out the absolute latency for total

Perhaps we could add a way to annotate the constant directly? Like total = 0'0

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Research direction

No source file or test is named. Start with the TreeAdder example and trace how int zero'0 = 0 establishes total's absolute latency, then compare that behavior with the proposed total = 0'0 syntax. Done means the latency-annotation behavior is defined and covered by an appropriate test.

Written by the indexing model from the issue text.

Assessment

Tech stack
rust
Domain
compilers
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
30/100

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