Annotations to modules, operators, and declarations that are passed to the generated SV or VHDL code
Open
Nobody has claimed this yet.
enhancement
- Dominant language
- Rust
- Stars
- 126
- Forks
- 6
- PR merge metrics
- No merged PRs in 30d
Description
HDL synthesis tools have many little attributes that can be attached to statements in SV or VHDL. These tell the compiler to implement a memory block with a given type of memory primitive, or to use DSPs vs LUTs for implementing multipliers
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
No files, tests, or implementation entry points are named. Start by clarifying how annotations should be represented and attached to modules, operators, and declarations, then inspect the generated SV or VHDL code to define the expected output and scope.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100