Enable unidirectional links
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- Dominant language
- C++
- Stars
- 19
- Forks
- 5
- PR merge metrics
- No merged PRs in 30d
Description
Currently by default the links are configured as bidirectional.
In some applications only one direction is needed. This would save some resources, especially the BRAMs needed for the second RX FIFO.
The aurora IP supports this mode with the Dataflow-Mode flag.
https://docs.amd.com/r/en-US/pg074-aurora-64b66b/Dataflow-Mode
Implementation would require to pass through a new config flag, change the verilog code to instantiate a send and recv variant and adapt the test example, so it uses only a send or a recv kernel per FPGA.
Contributor guide
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reading the Aurora IP Dataflow-Mode documentation and tracing the existing configuration flag through the Verilog implementation. Then inspect the test example and determine how it should use only a send or receive kernel per FPGA. Done means the new mode is configurable, instantiates the appropriate send/receive variant, and the example reflects unidirectional links.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100