Need a way to designate sim-only files from the local project

For testing, we want to have simulation-only entities in the same project that we swap for real IP in synthesis/FPGA build. One example of this is for testing/simulating the Versal NoC. We want to be able to swap between our own NMU/NSU entities (units for sending and receiving on the NoC) for simulation and the XPM IP cores for FPGA builds, because the XPM IP cores provided by Vivado require use of their simulator.

The only avenue to designate files sim-only at the moment is via bringing them in as an external library in vw.toml as we do here and then binding them via component with a synthesis directive as done here. This solution works if the IP has no dependence on any libraries other than the standard ones, but it is not the most clear that the entity itself is sim-only entity.

We briefly discussed and @rcgoodfellow suggested the following options:
• having some kind of marker at the top of a file like -- #vw(sim-only)
• having something in vw.toml
• having sim-only sources live in some particular subfolder by convention

Start by reading the external-library configuration in vw.toml and the synthesis directive in hdl/nmu_inst_wrap.vhd, then compare how local project sources are discovered. Review the three proposed approaches in the issue before choosing a design. Done means a project can clearly mark simulation-only sources and select them for simulation without making synthesis/FPGA builds use them.